7800 Software Guide
Contents
INTRODUCTION
The 7800 is a product which combines the ATARI 2600 hardware with a new graphics chip called MARIA. The entire 2600 library of cartridges will run on the 7800 as they do on the 2600, but new cartridges designed to access the improved hardware will be able to take advantage of a large number of improvements.
OVERVIEW OF THE 7800
Ignoring the 2600 environment, which is identical to the ATARI 2600, the 7800 environment is characterized by the following:
- (2) 6116's
- 4K bytes of RAM
- 6532
- I/O
- TIA
- sounds
- some input ports.
- Expanded cartridge slot
- SALLY (6502)
- microprocessor running at 1.79 MHz.
- MARIA
- all video
Additionally, there is a protection circuit which verifies that each cartridge has the correct encrypted data before enabling 7800 mode. Encryption will be covered in another document, but see Appendix 1, 7800 Memory Map, for information about reserving space for encryption.
6116's
There are two (2) 6116 2Kx8 RAM chips on the 7800 PC board. Together they occupy addresses 0x1800 to 0x27FF. They are also partly accessible (shadowed) at addresses 0x0040 visibleKangaroo" mode is on). In 320B mode, which is a 320x2 display mode, only the most significant palette bit is read. This means that either palette zero (0) of palette four (4) is used. If "Kangaroo" mode is off, transparency will work differently for modes. Consider a pair of 320-size pixels which make up one 160-size pixel. If either pixel of the pair is off, it will not be transparent, but will take on background color instead. If both pixels are off, they will be transparent. With "Kangaroo" mode on, things work as one would expect them to work in this mode. Another factor concerning 320 modes is that the horizontal positioning still happens like 160 mode. This means that in 320 modes, objects can only be positioned in 2 pixel increments.
320C and 320D are display modes somewhat similar to 320B and 320A, respectively. They are what you would get if you changed WRITE mode without changing READ mode (such as changing modes during a scan line). If you were in 320A mode, and wanted to include a character with more colors on the line, changing modes would give you 320C mode. Likewise, changing from 320B on the fly would give you 320D mode. The way data is interpreted for 320C and 320D will be explained later on.
In 160x4 mode, again only the most significant palette bit is read (note that 160x4 and 320B share the same WRITE mode sense). Because there are more color bits than each palette can handle, the palettes are combined in 160x4 mode so you may choose between the combinations of 0-3 and 4-7. The net result of 160x4 mode is twelve (12) colors, where color one (1) is P0C1 or P4C1, two (2) is P0C2 or P4C2, five (5) is P1C1 or P5C1, six (6) is P1C2 or P5C2, etc. and colors 0, 4, 8, and 12 are transparent.
The CTRL register is arranged as follows:
| bit 7 | bit 6 | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 |
|---|---|---|---|---|---|---|---|
| Color Kill: 0=normal color, 1=no color burst signal | DMA Control: 0,1=TEST DO NOT USE, as it could break the console. 2=normal DMA. 3=no DMA | Character Width: 0=single byte characters, 1=double byte characters | Border Control: 0=black screen border, 1=BACKGRND color border | Kangaroo Mode: 0=regular transparency, 1=kangaroo mode with no transparency | Read Mode: 0=160A/160B 1=N/A 2=320B/320D 3=320A/320C | ||
The coding of graphics data is straightforward for most of these modes. In 160A mode, each pair of bits is arranged so that the leftmost pixel's color is specified by the most significant pair of bits, and the rightmost pixel by the least significant pair of bits.
bits 76 54 32 10
___ ___ ___ ___
pixels | | | | | | | |
|___| |___| |___| |___|
| | | |
| | | |
| | | | 160x2
| | | |
| | | |
/ \ / \ / \ / \
_|___|___|___|___|___|___|___|_
graphics | | | | | | | | |
byte |___|___|___|___|___|___|___|___|
In 160B mode, the data is read as follows: the left pixel's color is specified by bits 3,2,7,6 (where 3 is MSB, 6 is LSB). The right pixel is specified by bits 1,0,5,4 (where 1 is MSB, 4 is LSB).
bits 3276 1054
___ ___
pixels | | | |
|___| |___|
| |
+---------------+ |
| | | 160x4
| +---------------+
| | | |
/ \ / \ / \ / \
_|___|___|___|___|___|___|___|_
graphic | | | | | | | | |
byte |___|___|___|___|___|___|___|___|
320A mode is a direct mapping like 160x2, except that each bit specifies the color of one pixel. Note that while the table illustrates the bit to pixel relationship with different colors for each pixel+bit pair, 320A is a monochrome mode.
bits 7 6 5 4 3 2 1 0
_______________________________
pixels | | | | | | | | |
|___|___|___|___|___|___|___|___|
| | | | | | | |
| | | | | | | |
| | | | | | | | 320A(x1)
| | | | | | | |
_|___|___|___|___|___|___|___|_
graphics | | | | | | | | |
byte |___|___|___|___|___|___|___|___|
The 320 modes get more complicated as we go on. The 320B mode bit to pixel mapping works as follows:
bits 73 62 51 40
___ ___ ___ ___
pixels | | | | | | | |
|___| |___| |___| |___|
|\ / \ / \ /|
| \ / \ / \ / |
| \ / \ / \ / |
| \ / \ \ / |
| / / \ \ |
| | \ / \ / | |
| | \ / \ / | |
| | \ / \ / | | 320B(x2)
| | / \ | |
| | | \ / | | |
| | | \ / | | |
| | | \ / | | |
| | | \ / | | |
| | | / | | |
| | | / \ | | |
_|___|___|___|___|___|___|___|_
graphics | | | | | | | | |
byte |___|___|___|___|___|___|___|___|
320C mode allows more colors than 320A, but cannot really be called 320x2. In this mode, some of the graphics data goes to specifying palettes, which is somewhat non-standard. If a pixel is on, it is color two (2), and if it is off, it is transparent, or background color (same as 320A and 320B). The palette is determined by combining the most significant palette. The palette for the leftmost pixel is specified by P2,D3, and D2 (where P means a palette bit, and D means graphics data bit), and the graphics are specified by D7. The next pixel right uses the same palette, and uses D6 for data. The next pixel right uses a palette specified by P2, D1, and D0, and uses D5 for data. The rightmost pixel uses the same palette, but D4 for data. The mapping for 320C mode is as follows:
palette
bits <P2><D3><D2> <P2><D1><D0>
\__________/ \__________/
color | /
bits D7 D6 D5 D4 | /
| /
pixels _ _ _ _ | /
| | | | | | | | | /
|_| |_| |_| |_| | /
| | | | | |
| | | | | | 320C
| | | | / \ / \
graphics _|___|___|___|___|___|___|___|_
byte | | | | | | | | |
|___|___|___|___|___|___|___|___|
320D mode is a little confusing, too. Every pixel refers to the same palette but palette bits affect the color of the pixels. The only palette bit used for palette definition is the most significant bit (same as 320B), so only palettes zero (0) and four (4) will be referenced. For color selection there is really more than one bit per pixel. The graphics data bits are used as follows: each is the most significant bit for a two bit pair. But the least significant bit of this pair is either P0 or P1 (where P again means palette bit).
If the specified palette is 0 or 4 (where P1 and P0 are zero), this is a normal 320x1 mode, like 320A. But if the specified palette is 5, palette 4 will be used, and certain pixels will be either color 1 or 3, and others will be 0 or 2. A picture is worth a thousand words, so:
palette
bits P2 P2 P2 P2 P2 P2 P2 P2
color DP DP DP DP DP DP DP DP
bits 71 60 51 40 31 20 11 00
_______________________________
pixels | | | | | | | | |
|___|___|___|___|___|___|___|___|
| | | | | | | |
| | | | | | | |
| | | | | | | | 320D
| | | | | | | |
_|___|___|___|___|___|___|___|_
graphics | | | | | | | | |
byte |___|___|___|___|___|___|___|___|
OVERVIEW OF TIA
Sound
In TIA there are two audio circuits for generating sound. They are identical but completely independent and can be operated simultaneously to produce sound effects through the TV speaker. Each audio circuit has three registers that control a noise-tone generator (what kind of sound), a frequency selection (high or low pitch of the sound), and a volume control.
Tone
The noise-tone generator is controlled by writing to the 4 bit audio control registers (AUDC0, AUDC1). The values written cause different kinds of sounds to be generated. Some are pure tones like a flute, others have various "noise" content like a rocket, motor, or explosion. Even though the TIA hardware manual lists the sounds created by each value, some experimentation will be necessary to find "your sound".
Frequency
Frequency selection is controlled by writing to a 5 bit audio frequency register (AUDF0, AUDF1). The value written is used to divide a 30KHz reference frequency creating a higher or lower pitch of whatever type of sound is created by the noise-tone generator. By combining the pure tones available from the noise-tone generator with frequency selection, a wide range of tones can be generated.
Volume
Volume is controlled by writing to a 4 bit audio volume register (AUDV0, AUDV1). Writing 0 to these registers turns sound off completely, and writing any value up to 15 increases the volume accordingly.
Registers
AUDF0/1 ($17/$18)
These addresses write data into the audio frequency divider registers.
| bit 4 | bit 3 | bit 2 | bit 1 | bit 0 | 30 KHz base frequency... |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | divided by 1 |
| 0 | 0 | 0 | 0 | 1 | divided by 2 |
| 0 | 0 | 0 | 1 | 0 | divided by 3 |
| ... | ... | ... | ... | ... | ... |
| 1 | 1 | 1 | 0 | 1 | divided by 30 |
| 1 | 1 | 1 | 1 | 0 | divided by 31 |
| 1 | 1 | 1 | 1 | 1 | divided by 32 |
AUDC0/1 ($15/$16)
These addresses write data into the audio control registers which control the noise content and additional division of the audio output.
| bit 3 | bit 2 | bit 1 | bit 0 | sound basis (divisor size, polycounter size) |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | divided by 1 |
| 0 | 0 | 0 | 1 | 4-bit poly |
| 0 | 0 | 1 | 0 | divided by 15, 4-bit poly |
| 0 | 0 | 1 | 1 | 5-bit poly to 4-bit poly |
| 0 | 1 | 0 | 0 | divided by 2. pure |
| 0 | 1 | 0 | 1 | divided by 2. pure |
| 0 | 1 | 1 | 0 | divided by 31. pure |
| 0 | 1 | 1 | 1 | 5-bit poly, div 2 |
| 1 | 0 | 0 | 0 | 9-bit poly |
| 1 | 0 | 0 | 1 | 5-bit poly |
| 1 | 0 | 1 | 0 | divided by 31. pure |
| 1 | 0 | 1 | 1 | last 4-bits high |
| 1 | 1 | 0 | 0 | divided by 6. pure |
| 1 | 1 | 0 | 1 | divided by 6. pure |
| 1 | 1 | 1 | 0 | divided by 93. pure |
| 1 | 1 | 1 | 1 | 5-bit poly, div 6 |
AUDV0/1 ($19/$1A)
These addresses write data into the audio volume registers which set the pull down impedance driving the audio output pads.
| bit 3 | bit 2 | bit 1 | bit 0 | audio output current |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | no output current |
| 0 | 0 | 0 | 1 | lowest output current |
| 0 | 0 | 1 | 0 | next to lowest output current |
| ... | ... | ... | ... | ... |
| 1 | 1 | 1 | 0 | next to highest output current |
| 1 | 1 | 1 | 1 | highest output current |
Input Ports INPT0/1/2/3
The TIA input ports are used for joystick fire buttons, reading paddle positions, and the keyboard controller. See the "Port A - Hand Controllers" section of the 6532 Overview for more detail.
OVERVIEW OF 6532
The I/O Ports
The two ports (Port A and Port B) are 8 bits wide and can be set for either input or output. Port A is used to interface to various hand-held controllers but Port B is dedicated to reading the status of the console switches and joystick buttons.
Port B - Console Switches and Joystick Buttons - SWCHB ($282)
Port B is read by addressing SWCHB (HEX 282) to determine the status of all the console switches according to the following table:
| bit 7 | bit 6 | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 |
|---|---|---|---|---|---|---|---|
| P1 difficulty switch. 0=(B)asic, 1=(A)dvanced | P0 difficulty switch. 0=(B)asic, 1=(A)dvanced | none | none | Pause. 0=pressed, 1=released | none | Game Select. 0=pressed, 1=released | Game Start. 0=pressed, 1=released |
Bits 2 and 4 are used to enable/disable the 2-button joystick mode. More details on this are in the Joystick Controllers section.
====Port A t make a difference), the HALT input will be enabled.
APPENDIX 1: 7800 MEMORY MAP
The memory map of the 7800, graphically illustrated on the next page, is in many ways similar to that of the 2600, with the addition not only of MARIA, but also of 4K of RAM. This RAM is shadowed (responds to other addresses) in zero, first, second, and third pages, the first two of these being significant. You will notice the absence of the 128 bytes of 6532 RAM that make up zero page RAM in the 2600. This is because of a speed discrepancy with the 6532. It's RAM has moved to an area in page four (4) and may not exist in future versions of the MARIA chip, so it should not be used.
| From | To | ||
|---|---|---|---|
| 1 | TIA | 0000 00XX 0000 0000 | 0000 00XX 0001 1111 |
| 2 | MARIA | 0000 00XX 0010 0000 | 0000 00XX 0011 1111 |
| 3 | 6532 Ports | 0000 001X 1XX0 0000 | 0000 001X 1XX1 1111 |
| 4 | 6532 RAM (don't use) | 0000 010X 1000 0000 | 0000 010X 1111 1111 |
| 5 | RAM | 0001 1000 0000 0000 | 0010 0111 1111 1111 |
| 6 | RAM Shadow | 00X0 000A 0100 0000 | 00X0 000A 1111 1111 |
| 7 | RAM Shadow | 0010 X000 0000 0000 | 0010 X111 1111 1111 |
Where X means "Don't Care", and A means the bits may be 1 or 0, but are not ignored. Entries 5 and 6 indicate that pieces of RAM from 0x1800 - 0x27FF appear in zero, and first pages. The last entry indicates that the last 2K block (0x2000 - 0x27FF) is repeated at 0x2800. For encryption purposes, the 120 bytes from 0xFF80 - 0xFFF7 must be left free. Put FFs in this area until encrypted.
| Locations | Device |
|---|---|
| 0000 to 001F | TIA Registers |
| 0020 to 003F | MARIA Registers |
| 0040 to 00FF | RAM (6116 Block Zero) |
| 0100 to 013F | Shadow of Page 0 |
| 0140 to 01FF | RAM (6116 Block One) |
| 0200 to 027F | Shadowed |
| 0280 to 02FF | 6532 Ports |
| 0300 to 037F | Shadowed |
| 0380 to 03FF | Shadowed 6532 Ports |
| 0400 to 047F | Available for mapping by external devices |
| 0480 to 04FF | 6532 RAM. Don't Use |
| 0500 to 057F | Available for mapping by external devices |
| 0580 to 05FF | 6532 RAM Shadow. Don't Use |
| 0600 to 17FF | Available for mapping by external devices |
| 1800 to 203F | RAM |
| 2040 to 20FF | Block Zero Shadow |
| 2100 to 213F | RAM |
| 2140 to 21FF | Block One Shadow |
| 2200 to 27FF | RAM |
| 2800 to 2FFF | Unavailable for mapping by external devices. (BIOS conflict) |
| 3000 to FF7F | Available for mapping by external devices |
| FF80 to FFF7 | Reserved for cart encryption signature |
| FFF8 to FFFF | Reserved for startup flags and 6502 vectors |
APPENDIX 2: STANDARD 7800 EQUATES
;****** 00-1F ********* TIA REGISTERS ****************** INPTCTRL = $01 ;Input control write-only INPT0 = $08 ;Paddle Control Input 0 read-only INPT1 = $09 ;Paddle Control Input 1 read-only INPT2 = $0A ;Paddle Control Input 2 read-only INPT3 = $0B ;Paddle Control Input 3 read-only ; ** some common alternate names for INPT0/1/2/3 INPT4B = $08 ;Joystick 0 Fire 0 read-only INPT4A = $09 ;Joystick 0 Fire 1 read-only INPT5B = $0A ;Joystick 1 Fire 0 read-only INPT5A = $0B ;Joystick 1 Fire 1 read-only INPT4R = $08 ;Joystick 0 Fire 0 read-only INPT4L = $09 ;Joystick 0 Fire 1 read-only INPT5R = $0A ;Joystick 1 Fire 0 read-only INPT5L = $0B ;Joystick 1 Fire 1 read-only INPT4 = $0C ;Player 0 Fire Button Input read-only INPT5 = $0D ;Player 1 Fire Button Input read-only AUDC0 = $15 ;Audio Control Channel 0 write-only AUDC1 = $16 ;Audio Control Channel 1 write-only AUDF0 = $17 ;Audio Frequency Channel 0 write-only AUDF1 = $18 ;Audio Frequency Channel 1 write-only AUDV0 = $19 ;Audio Volume Channel 0 write-only AUDV1 = $1A ;Audio Volume Channel 1 write-only ;****** 20-3F ********* MARIA REGISTERS *************** BACKGRND = $20 ;Background Color write-only P0C1 = $21 ;Palette 0 - Color 1 write-only P0C2 = $22 ;Palette 0 - Color 2 write-only P0C3 = $23 ;Palette 0 - Color 3 write-only WSYNC = $24 ;Wait For Sync write-only P1C1 = $25 ;Palette 1 - Color 1 write-only P1C2 = $26 ;Palette 1 - Color 2 write-only P1C3 = $27 ;Palette 1 - Color 3 write-only MSTAT = $28 ;Maria Status read-only P2C1 = $29 ;Palette 2 - Color 1 write-only P2C2 = $2A ;Palette 2 - Color 2 write-only P2C3 = $2B ;Palette 2 - Color 3 write-only DPPH = $2C ;Display List List Pointer High write-only P3C1 = $2D ;Palette 3 - Color 1 write-only P3C2 = $2E ;Palette 3 - Color 2 write-only P3C3 = $2F ;Palette 3 - Color 3 write-only DPPL = $30 ;Display List List Pointer Low write-only P4C1 = $31 ;Palette 4 - Color 1 write-only P4C2 = $32 ;Palette 4 - Color 2 write-only P4C3 = $33 ;Palette 4 - Color 3 write-only CHARBASE = $34 ;Character Base Address write-only P5C1 = $35 ;Palette 5 - Color 1 write-only P5C2 = $36 ;Palette 5 - Color 2 write-only P5C3 = $37 ;Palette 5 - Color 3 write-only OFFSET = $38 ;Unused - Store zero here write-only P6C1 = $39 ;Palette 6 - Color 1 write-only P6C2 = $3A ;Palette 6 - Color 2 write-only P6C3 = $3B ;Palette 6 - Color 3 write-only CTRL = $3C ;Maria Control Register write-only P7C1 = $3D ;Palette 7 - Color 1 write-only P7C2 = $3E ;Palette 7 - Color 2 write-only P7C3 = $3F ;Palette 7 - Color 3 write-only ;****** 280-2FF ******* PIA PORTS AND TIMERS ************ SWCHA = $280 ;P0, P1 Joystick Directional Input read-write SWCHB = $282 ;Console Switches read-write CTLSWA = $281 ;I/O Control for SCHWA read-write SWACNT = $281 ;VCS name for above read-write CTLSWB = $283 ;I/O Control for SCHWB read-write SWBCNT = $283 ;VCS name for above read-write INTIM = $284 ;Iterval Timer Read read-only TIM1T = $294 ;Set 1 CLK Interval (838 nsec/interval) write-only TIM8T = $295 ;Set 8 CLK Interval (6.7 usec/interval) write-only TIM64T = $296 ;Set 64 CLK Interval (63.6 usec/interval) write-only T1024T = $297 ;Set 1024 CLK Interval (858.2 usec/interval) write-only TIM64TI = $29E ;Interrupt timer 64T write-only
APPENDIX 3: DMA TIMING
There is some uncertainty as to the number of cycles DMA will require, because the internal MARIA chip timing resolution is 7.16 MHz, while the 6502 runs at either 1.79 MHz or 1.19MHz. As a result, it is not known how many extra cycles will be needed in DMA startup/shutdown to make the 6502 happy.
It is even possible for the 6502 to be in the middle of a long (TIA or 6532) access when it is to be halted, so the uncertainty goes up to about 5 cycles.
All times listed below refer to 7.16 MHz cycles.
| Event | MARIA Cycle Cost | Comments |
|---|---|---|
| DMA start-up and shutdown, last line in zone | 24 cycles | The DMA start-up may be delayed if the 6502 clock isn't at the end of a cycle when DMA begins. Up to 3 additional cycles are lost for DMA if the 6502 is at normal speed, or up to 5 additional cycles are lost if the 6502 happens to be slowed down for TIA access. DMA start-up delay usually occurs every other scanline, since a scanline length is 113.5 6502 cycles long. |
| DMA start-up and shutdown, other lines in zone | 16 cycles | |
| process 4-byte DL header | 8 cycles | |
| process 5-byte DL header | 10 cycles | |
| direct graphics data read | 3 cycles | per byte of data read |
| indirect 1-byte read | 6 cycles | |
| indirect 2-byte read | 9 cycles |
If holey DMA is enabled and graphics reads would reside in a DMA hole, only 3 cycles of penalty for the graphic read is incurred, whatever the sprite width is.
The end of VBLANK is made up of a DMA startup plus a Long shutdown.
DMA does not begin until 7 CPU (1.79 MHz) cycles into each scan line. The significance of this is that there is enough time to change a color, or change CTRL before DMA begins, and during HBLANK (before display begins). This figure should, however, be included in any DMA usage calculations.
Another timing consideration is there is one MPU (7.16 MHz) cycle between DMA shutdown and generation of a DLI.
APPENDIX 4: FRAME TIMING
33.5 cycles @1.79 MHz 80 cycles @1.79 MHz
134 cycles @7.16 MHz 320 cycles @7.16 MHz
NTSC <--67 pixels--> <-----------160 pixels-------------> PAL
______|_______________|____________________________________|_____
^ | | ^ | ^
| | | | | |
16 |<---HBLANK---->| VBLANK | 16
| | | | | |
| | | | | |
______v____|_______________|__________________v_________________|___v______
^ ^ | | ^ | ^ ^
| | | | | | | |
| 25 | | | | 25 |
| | | | | | | |
| | | | | | | |
| -v----|---------------|------------------|-----------------|---v- |
| ^ | | | | ^ |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
243 192 | | VISIBLE | 242 293
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| -v----|---------------|------------------|-----------------|---v- |
| ^ | | | | ^ |
| | | | | | | |
| 26 | | | | 26 |
| | | | | | | |
| | | | | | | |
_v____v____|_______________|__________________v_________________|___v____v_
^ | | ^ | ^
| | | | | |
4 | | VBLANK | 4
| | | | | |
| | | | | |
_v____|_______________|__________________v_________________|___v_
|<-------------------227 pixels--------------------->|
| 454 cycles @7.16 Mhz |
113.5 cycles @1.79 MHz
