POKEY C012294 Documentation
- 1 General Description
- 2 Audio
- 2.1 Audio Filters
- 2.2 AUDCTL (Audio Control (08)
- 2.3 AUDF1-4 (Audio Frequency)(00,02,04,06)
- 2.4 AUDC1-4 (Audio Channel Control)(01,03,05,07)
- 2.5 PITCH VALUES FOR THE MUSICAL NOTES - AUDCTL=0, AUDC=$AX
- 3 Keyboard Scan
- 4 Potentiometer Ports
- 5 Timers
- 6 Random Number Generator
- 7 Serial Port
- 8 IRQ interrupts
There are four semi-independent audio channels, each with its own frequency, noise and volume control. Each channel has an eight-bit "divide-by-N" frequency divider and an eight-bit control register, which selects the noise (polynomial counter) content and volume.
There are six key scan line (K0-K5), which holds a value from 00 to 3F. There are two sense lines. One of the sense lines is for the full decode of the six scan lines. The other sense line is for decoding only the codes (CTRL, SHIFT and BREAK key).
There are eight pot ports for measuring input rise time. Each input has an eight-bit counter which is clocked every TV line. Each input also has a dump transistor which is turned on or off by software.
There are three timer which use the audio channels. If start timer (STIMER) is enabled, the audio channels are reset.
There is a Random Number Generator which is eight bits from a polynomial counter.
There is a serial I/O port. The serial port consists of a serial output line, a serial input line, a serial output clock line, and a bi-directional serial data clock line. Also, there are control register which are used to configure the serial port.
There are eight IRQ interrupt. They are BREAK key, OTHER key, SERIAL INPUT READY, SERIAL OUTPUT NEEDED, TRANSMISSION FINISHED, TIMER #4, TIMER #2 and TIMER #1. These interrupts can be enabled or disabled by software. There is also a register to read interrupt status.
There are four semi-independent audio channels, each with its own frequency, noise and volume control. Each channel has an eight-bit "divide-by-N" frequency divider and an eight-bit control register (AUDFX). Each channel also has an eight-bit control register (AUDCX) which selects the noise (polynomial counter) content and the volume.
All four frequency dividers can be clocked simultaneously from 64 kHz or 15 kHz by AUDCTL bit 0. Frequency dividers 1 and 3 can alternately be clocked from the CPU clock (1.79 MHz NTSC, 1.77 MHz PAL) by setting AUDCTL bits 5 and 6. Frequency dividers 2 and 4 can alternately be clocked with the output of dividers 1 and 3 by setting AUDCTL bits 4 and 3. This allows the following options: 4 channels of 8-bit resolution, 2 channels of 16-bit resolution, or 1 channel of 16-bit resolution and 2 channels of 8-bit resolution.
There are three polynomial counters (17 bit, 5 bit and 4-bit) used to generate randowm noise. The 17-bit poly counter can be reduced to a 9-bit poly counter by bit 7 of AUDCTL. These counters are clocked byt 1.79 MHz. Their outputs, however, can be sampled independently by the four audio channels at a rate determined by each channel's frequency divider. Thus each channle appears to contain seperate poly counters clocked at its own frequency. This oly counter noise sampling is controlled by bits 5, 6 and 7 of each AUDCX register. Because the poly counters are sampled by the "divide-by-N" frequency divider, the output obviously cannot change faster than the sampling rate. In these modes (poly noise outputted), the dividers are therefore acting as "low-pass" filter clocks, allowing only the low-frequency noise to pass.
The output of the noise-control circuit described above consists of pure tones (square wave type), or polynomial counter noise at a maximum frequency set by the "divide-by-N" counter (low pass clock). This output can be routed through a high-pass filter if desired by use of bits 1 and 2 of AUDCTL.
The high-pass filter consists of a D-type flip-flop and an exclusive-OR gate. The noise control circuit output is sampled by this flip flop at a rate set by the "high-pass" clock. The input and output of the flip-flop pass through the exclusive-OR gate. However, if it is lower than the clock rate, the flip-flop output will tend to follow the input and the two exclusive-OR gate inputs will mostly be identical (11 or 00) givving very littl output. This gives the effect of a crude high-pass filter, passing only noise whose minimum frequency is set by the high-pass clock rate. Only channels 1 and 2 have such a high-pass filter. The high-pass clock for channel 1 comes from the channel 3 divider. The high-pass clock for channel 2 comes from the channel 4 divider. This filter is only included if bit 1 or 2 of AUDCTL is true.
A volume control ciruit is placed at the output of each channel. This is a crude 4-bit digital to analog converter that allows sellection of one of 16 possible output current levels for a true audio input. A logic zero audio input to this voulme circuit always gives an open-circuit (zero current) output. The volume selection is controlled by bits 0 through 3 of AUDCX. "Volume Control only" mode can be invoked by forcing this circuit's audio input true with bit 4 of AUDCX. In this mode the dividers, noise counters, and filter circuits are all disconnected from the channel output. Only the volume control bits (0 to 3 of AUDCX) determine the channel output current.
The audio output of any channel can be completely turned off by writing zero to the volume control bits of AUDCX. All ones give maximum volume.
Any channel noise output (without high-pass filter)
Channel 1 noise output (with high-pass filter)
Channel 2 noise output (with high-pass filter)
AUDCTL (Audio Control (08)
|bit 7||bit 6||bit 5||bit 4||bit 3||bit 2||bit 1||bit 0|
|makes the 17-bit poly counter into a 9-bit poly counter.||clocks channel 1 with 1.79 MHz, instead of 64 kHz||clocks channel 3 with 1.79 MHz, instead of 64 kHz||clock channel 2 with channel 1, instead of 64 kHz (16-bit)||clock channel 4 with channel 3, instead of 64 kHz (16-bit)||inserts high-pass filter into channel 1, clocked by channel 3 (see section 2)||inserts high-pass filter into channel 2, clocked by chan 4||change normal clock base from 64 kHz to 15 kHz|
The frequencies given above are approximate. The exact frequency (Fin) that clocks the divide-by-N counters is given below (NTSC only, PAL is different).
|Fin Approximate||Fin Exact||Notes|
|1.79 MHz||1.78979 MHz||Use modified formula for Fout|
|64 KHz||63.9210 KHz|
|15 kHz||15.6999 kHz||Use normal formula for Fout|
The Normal formula for the output frequency is: Fout = Fin /2N, where
- N = the binary number in the frequency register (AUDF), plus 1 (N=AUDF+1).
The Modified formula should be used when Fin = 1.79 MHz and a more exactl result is desired: Fout = Fin /2(AUDF+M), where
- M = 4 if 8 bit counter (AUDCTL bit 3 or 4 = 0),
- M = 7 if 16 bit counter (AUDCTL bit 3 or 4 = 1)
AUDF1-4 (Audio Frequency)(00,02,04,06)
These addresses write data into each of the four Audio Frequency Control Registers. Each register controls a divide-by-N counter, where N is the value written to the register AUDF(X), plus 1.
AUDC1-4 (Audio Channel Control)(01,03,05,07)
These addresses write data into each of the four Audio Control Registers. Each register controls the noise content and volume of the corresponding Audio Channel.
|bit 7||bit 6||bit 5||bit 4||bit 3||bit 2||bit 1||bit 0||Effect|
|0||0||0||0||Volume Level||17 Bit poly - 5 Bit poly - N|
|0||0||1||0||Volume Level||5 Bit poly - N - 2|
|0||1||0||0||Volume Level||4 Bit poly - 5 Bit poly - N|
|0||1||1||0||Volume Level||5 Bit poly - N - 2|
|1||0||0||0||Volume Level||17 Bit poly - N|
|1||0||1||0||Volume Level||Pure Tone - N - 2|
|1||1||0||0||Volume Level||4 Bit poly - N|
|-||-||-||1||Volume Level||Force Output Volume only|
PITCH VALUES FOR THE MUSICAL NOTES - AUDCTL=0, AUDC=$AX
|Note||AUDF Hex||AUDF Dec|
|A# or Bb||21||33|
|G# or Ab||25||37|
|F# or Gb||2A||42|
|D# or Eb||32||50|
|C# or Db||39||57|
|A# or Bb||44||68|
|G# or Ab||4C||76|
|F# or Gb||55||85|
|D# or Eb||66||102|
|C# or Db||72||114|
|A# or Bb||88||136|
|G# or Ab||99||153|
|F# or Gb||AD||173|
|D# or Eb||CC||204|
|C# or Db||E6||230|
POKEY Keyboard lines not connected on the 7800
POKEY Potentiometer lines not connected on the 7800
POKEY IRQ not connected on the 7800
Random Number Generator
There is a seventeen bit polynomial counter that the CPU can read eight bits from. The polynomial counter can be changed to nine bits by use of AUDCTL. If the POKEY is in the initial state (see SKTLS), the counter is set to all ones state, therefore the CPU will read $FF.
RANDOM (Random Number Generator) (0A):
This address reads the high-order eight bits of a polynomial counter (nine bits if bit 7 of AUDCTL = 1).